EP1C12F100I7 datasheet(26/94 Pages) ALTERA

26 / 94 page

26

Altera Corporation

Cyclone FPGA Family Data Sheet

Preliminary Information

Data is written into each address location at the falling edge of the clock

and read from the address at the rising edge of the clock. The shift register

mode logic automatically controls the positive and negative edge clocking

to shift the data in one clock cycle. Figure 14 shows the M4K memory

block in the shift register mode.

Figure 14. Shift Register Memory Configuration

m-Bit Shift Register

w

m-Bit Shift Register

w

× m × n Shift Register

n Number

of Taps

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