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EP1C12F100I7 Datasheet(PDF) 20 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 20 Page - Altera Corporation |
20 / 94 page ![]() 20 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Figure 10. LUT Chain & Register Chain Interconnects The C4 interconnects span four LABs or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 11 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including PLLs, M4K memory blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. LE 1 LE 2 LE 3 LE 4 LE 5 LE 6 LE 7 LE 8 LE 9 LE 10 LUT Chain Routing to Adjacent LE Local Interconnect Register Chain Routing to Adjacent LE's Register Input Local Interconnect Routing Among LEs in the LAB |
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