Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

EP1C12F100I7 Datasheet(PDF) 1 Page - Altera Corporation

Part # EP1C12F100I7
Description  Cyclone FPGA Family
Download  94 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I7 Datasheet(HTML) 1 Page - Altera Corporation

  EP1C12F100I7 Datasheet HTML 1Page - Altera Corporation EP1C12F100I7 Datasheet HTML 2Page - Altera Corporation EP1C12F100I7 Datasheet HTML 3Page - Altera Corporation EP1C12F100I7 Datasheet HTML 4Page - Altera Corporation EP1C12F100I7 Datasheet HTML 5Page - Altera Corporation EP1C12F100I7 Datasheet HTML 6Page - Altera Corporation EP1C12F100I7 Datasheet HTML 7Page - Altera Corporation EP1C12F100I7 Datasheet HTML 8Page - Altera Corporation EP1C12F100I7 Datasheet HTML 9Page - Altera Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 94 page
background image
®
Altera Corporation
1
Cyclone
FPGA Family
March 2003, ver. 1.1
Data Sheet
DS-CYCLONE-1.1
Introduction
Preliminary
Information
The CycloneTM field programmable gate array family is based on a 1.5-V,
0.13-
µm, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,
32-bit peripheral component interconnect (PCI), for interfacing with and
supporting ASSP and ASIC devices. Altera also offers new low-cost serial
configuration devices to configure Cyclone devices.
Features...
2,910 to 20,060 LEs, see Table 1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66-MHz, 32-bit PCI standard
Low speed (311 Mbps) LVDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
AlteraMegaCorefunctions and Altera Megafunctions Partners
Program (AMPPSM) megafunctions
Note to Table 1:
(1)
This parameter includes global clock pins.
Table 1. Cyclone Device Features
Feature
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
LEs
2,910
4,000
5,980
12,060
20,060
M4K RAM blocks (128
× 36 bits)
131720
5264
Total RAM bits
59,904
78,336
92,160
239,616
294,912
PLLs
12
222
Maximum user I/O pins (1)
104
301
185
249
301


Similar Part No. - EP1C12F100I7

ManufacturerPart #DatasheetDescription
logo
Altera Corporation
EP1C12F100I7ES ALTERA-EP1C12F100I7ES Datasheet
1Mb / 104P
   Cyclone FPGA Family Data Sheet
More results

Similar Description - EP1C12F100I7

ManufacturerPart #DatasheetDescription
logo
Altera Corporation
EP1C20F ALTERA-EP1C20F Datasheet
1Mb / 106P
   Cyclone FPGA Family
EP1C3 ALTERA-EP1C3 Datasheet
1Mb / 104P
   Cyclone FPGA Family Data Sheet
EP4CE115F29I7N ALTERA-EP4CE115F29I7N Datasheet
372Kb / 14P
   Cyclone IV FPGA Device Family
EP4CE10E22C8N ALTERA-EP4CE10E22C8N Datasheet
498Kb / 14P
   Cyclone IV FPGA Device Family Overview
EP4CE6E22I7N ALTERA-EP4CE6E22I7N Datasheet
498Kb / 14P
   Cyclone IV FPGA Device Family Overview
EP4CE6E22C8 ALTERA-EP4CE6E22C8 Datasheet
498Kb / 14P
   Cyclone IV FPGA Device Family Overview
EP4CE55F29I7 ALTERA-EP4CE55F29I7 Datasheet
372Kb / 14P
   Cyclone IV FPGA Device Family Overview
EP4CGX150CF23C8N ALTERA-EP4CGX150CF23C8N Datasheet
395Kb / 14P
   1. Cyclone IV FPGA Device Family Overview
EP4CE10F17I7N ALTERA-EP4CE10F17I7N Datasheet
498Kb / 14P
   1. Cyclone IV FPGA Device Family Overview
EP1C12Q240C8N ALTERA-EP1C12Q240C8N Datasheet
1Mb / 106P
   Section I. Cyclone FPGA Family Data Sheet
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com