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EP1C12F100I7 Datasheet(PDF) 91 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 91 Page - Altera Corporation |
91 / 94 page ![]() Altera Corporation 91 Preliminary Information Cyclone FPGA Family Data Sheet Maximum Input & Output Clock Rates Tables 67 and 68 show the maximum input clock rate for column and row pins in Cyclone devices. Table 66. Cyclone IOE Programmable Delays on Row Pins Parameter Setting -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit Min Max Min Max Min Max Decrease input delay to internal cells On 3,057 3,362 3,668 ps Small 2,212 2,433 2,654 ps Medium 2,639 2,902 3,166 ps Large 3,057 3,362 3,668 ps Decrease input delay to input register On 3,057 3,362 3,668 ps Increase delay to output pin On 556 611 667 ps Table 67. Cyclone Maximum Input Clock Rate for Column Pins I/O Standard -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit LVTTL 304 304 304 MHz 2.5 V 220 220 220 MHz 1.8 V 213 213 213 MHz 1.5 V 166 166 166 MHz LVCMOS 304 304 304 MHz SSTL-3 class I 100 100 100 MHz SSTL-3 class II 100 100 100 MHz SSTL-2 class I 134 134 134 MHz SSTL-2 class II 134 134 134 MHz LVDS 231 231 231 MHz |
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