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EP1C12F100I7 Datasheet(PDF) 90 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 90 Page - Altera Corporation |
90 / 94 page ![]() 90 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Note to Tables 59 − 64: (1) EP1C3 devices do not support the PCI I/O standard. Table 65 shows the adder delays for the IOE programmable delays. These delays are controlled with the Quartus II software options listed in the Parameter column. 1.8-V LVTTL 2 mA 6,606 7,267 7,927 ps 8 mA 5,112 5,623 6,134 ps 12 mA 4,862 5,348 5,834 ps 1.5-V LVTTL 2 mA 8,380 9,218 10,055 ps 4 mA 7,437 8,180 8,923 ps 8 mA 6,888 7,576 8,264 ps 3.3-V PCI 1,175 1,292 1,409 ps SSTL-3 class I 1,799 1,979 2,158 ps SSTL-3 class II 1,363 1,499 1,635 ps SSTL-2 class I 2,115 2,326 2,537 ps SSTL-2 class II 1,820 2,001 2,183 ps LVDS 1,330 1,463 1,595 ps Table 64. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2) I/O Standard -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit MinMax MinMax MinMax Table 65. Cyclone IOE Programmable Delays on Column Pins Parameter Setting -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit Min Max Min Max Min Max Decrease input delay to internal cells On 3,057 3,362 3,668 ps Small 2,212 2,433 2,654 ps Medium 2,639 2,902 3,166 ps Large 3,057 3,362 3,668 ps Decrease input delay to input register On 3,057 3,362 3,668 ps Increase delay to output pin On 552 607 662 ps |
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