EP1C12F100I7 datasheet(86/94 Pages) ALTERA

Part #	EP1C12F100I7

Description	Cyclone FPGA Family

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Manufacturer	ALTERA [Altera Corporation]

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86

Altera Corporation

Cyclone FPGA Family Data Sheet

Preliminary Information

Tables 59 through 64 show the adder delays associated with column and

row I/O pins for all packages. If an I/O standard is selected other than

LVTTL 24 mA with a fast slew rate, add the selected delay to the external

tCO and tSU I/O parameters shown in Tables 44 through 47.

Table 59. Cyclone I/O Standard Column Pin Input Delay Adders

I/O Standard

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

MinMax

LVCMOS

0

ps

3.3-V LVTTL

0

ps

2.5-V LVTTL

28

30

33

ps

1.8-V LVTTL

214

235

256

ps

1.5-V LVTTL

326

358

391

ps

SSTL-3 class I

−221

−244

−266

ps

SSTL-3 class II

−221

−244

−266

ps

SSTL-2 class I

−264

−291

−317

ps

SSTL-2 class II

−264

−291

−317

ps

LVDS

−197

−217

−237

ps

Table 60. Cyclone I/O Standard Row Pin Input Delay Adders

I/O Standard

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

MinMax

LVCMOS

0

ps

3.3-V LVTTL

0

ps

2.5-V LVTTL

28

30

33

ps

1.8-V LVTTL

214

235

256

ps

1.5-V LVTTL

326

358

391

ps

3.3-V PCI (1)

000

ps

SSTL-3 class I

−221

−244

−266

ps

SSTL-3 class II

−221

−244

−266

ps

SSTL-2 class I

−264

−291

−317

ps

SSTL-2 class II

−264

−291

−317

ps

LVDS

−197

−217

−237

ps

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