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EP1C12F100I7 Datasheet(PDF) 85 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 85 Page - Altera Corporation |
85 / 94 page ![]() Altera Corporation 85 Preliminary Information Cyclone FPGA Family Data Sheet Tables 57 through 58 show the external timing parameters on column and row pins for EP1C20 devices. External I/O Delay Parameters External I/O delay timing parameters for I/O standard input and output adders and programmable input and output delays are specified by speed grade independent of device density. Table 57. EP1C20 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit Min Max Min Max Min Max tINSU 2.226 2.406 2.585 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 3.926 2.000 4.358 2.000 4.795 ns tXZ 5.553 6.149 6.748 ns tZX 5.553 6.149 6.748 ns tINSUPLL 1.138 1.244 1.349 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 1.957 0.500 2.158 0.500 2.363 ns tXZPLL 3.584 3.949 4.316 ns tZXPLL 3.584 3.949 4.316 ns Table 58. EP1C20 Row Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit Min Max Min Max Min Max tINSU 2.361 2.561 2.763 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 3.774 2.000 4.184 2.000 4.597 ns tXZ 5.360 5.929 6.501 ns tZX 5.360 5.929 6.501 ns tINSUPLL 1.273 1.399 1.527 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPLL 0.500 1.805 0.500 1.984 0.500 2.165 ns tXZPLL 3.391 3.729 4.069 ns tZXPLL 3.391 3.729 4.069 ns |
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