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EP1C12F100I7 Datasheet(PDF) 80 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 80 Page - Altera Corporation |
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80 / 94 page  80 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Table 48 shows the external I/O timing parameters when using global clock networks. Notes to Table 48: (1) These timing parameters are sample-tested only. (2) These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II software to verify the external timing for any pin. Table 48. Cyclone Global Clock External I/O Timing Parameters Notes (1), (2) Symbol Parameter Conditions tINSU Setup time for input or bidirectional pin using IOE input register with global clock fed by CLK pin tINH Hold time for input or bidirectional pin using IOE input register with global clock fed by CLK pin tOUTCO Clock-to-output delay output or bidirectional pin using IOE output register with global clock fed by CLK pin CLOAD = 10 pF tXZ Synchronous column IOE output enable register to output pin disable delay using global clock fed by CLK pin CLOAD = 10 pF tZX Synchronous column IOE output enable register to output pin enable delay using global clock fed by CLK pin CLOAD = 10 pF tINSUPLL Setup time for input or bidirectional pin using IOE input register with global clock fed by Enhanced PLL with default phase setting tINHPLL Hold time for input or bidirectional pin using IOE input register with global clock fed by enhanced PLL with default phase setting tOUTCOPLL Clock-to-output delay output or bidirectional pin using IOE output register with global clock enhanced PLL with default phase setting CLOAD = 10 pF tXZPLL Synchronous column IOE output enable register to output pin disable delay using global clock fed by enhanced PLL with default phase setting CLOAD = 10 pF tZXPLL Synchronous column IOE output enable register to output pin enable delay using global clock fed by enhanced PLL with default phase setting CLOAD = 10 pF |
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