EP1C12F100I7 datasheet(79/94 Pages) ALTERA

79 / 94 page

Altera Corporation

79

Preliminary Information

Cyclone FPGA Family Data Sheet

Figure 38. External Timing in Cyclone Devices

All external I/O timing parameters shown are for 3.3-V LVTTL I/O

standard with the maximum current strength and fast slew rate. For

external I/O timing using standards other than LVTTL or for different

current strengths, use the I/O standard input and output delay adders in

Tables 59 through 63.

PRN

CLRN

DQ

PRN

CLRN

DQ

PRN

CLRN

DQ

Dedicated

Clock

Bidirectional

Output Register

Input Register

OE Register

tXZ

tZX

tINSU

tINH

tOUTCO

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