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EP1C12F100I7 Datasheet(PDF) 78 Page - Altera Corporation

Part # EP1C12F100I7
Description  Cyclone FPGA Family
Download  94 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I7 Datasheet(HTML) 78 Page - Altera Corporation

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Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
External Timing Parameters
External timing parameters are specified by device density and speed
grade. Figure 38 shows the timing model for bidirectional IOE pin timing.
All registers are within the IOE.
Table 46. M4K Block Internal Timing Microparameters
Symbol
-6
-7
-8
Unit
Min
Max
Min
Max
Min
Max
tM4KRC
4,379
5,035
5,691
ps
tM4KWC
2,910
3,346
3,783
ps
tM4KWERESU
72
82
93
ps
tM4KWEREH
43
49
55
ps
tM4KBESU
72
82
93
ps
tM4KBEH
43
49
55
ps
tM4KDATAASU
72
82
93
ps
tM4KDATAAH
43
49
55
ps
tM4KADDRASU
72
82
93
ps
tM4KADDRAH
43
49
55
ps
tM4KDATABSU
72
82
93
ps
tM4KDATABH
43
49
55
ps
tM4KADDRBSU
72
82
93
ps
tM4KADDRBH
43
49
55
ps
tM4KDATACO1
621
714
807
ps
tM4KDATACO2
4,351
5,003
5,656
ps
tM4KCLKHL
105
120
136
ps
tM4KCLR
286
328
371
ps
Table 47. Routing Delay Internal Timing Microparameters
Symbol
-6
-7
-8
Unit
Min
Max
Min
Max
Min
Max
tR4
261
300
339
ps
tC4
338
388
439
ps
tLOCAL
244
281
318
ps


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