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EP1C12F100I7 Datasheet(PDF) 74 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 74 Page - Altera Corporation |
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74 / 94 page  74 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worst- case voltage and junction temperature conditions. Internal Timing Parameters Internal timing parameters are specified on a speed grade basis independent of device density. Tables 40 through 43 describe the Cyclone device internal timing microparameters for LEs, IOEs, M4K memory structures, and MultiTrack interconnects. Table 39. Cyclone Device Timing Model Status Device Preliminary Final EP1C3 v EP1C4 v EP1C6 v EP1C12 v EP1C20 v Table 40. LE Internal Timing Microparameter Descriptions Symbol Parameter tSU LE register setup time before clock tH LE register hold time after clock tCO LE register clock-to-output delay tLUT LE combinatorial LUT delay for data-in to data-out tCLR Minimum clear pulse width tPRE Minimum preset pulse width tCLKHL Minimum clock high or low time |
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