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EP1C12F100I7 Datasheet(PDF) 73 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 73 Page - Altera Corporation |
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73 / 94 page  Altera Corporation 73 Preliminary Information Cyclone FPGA Family Data Sheet Notes to Tables 23 – 38: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Conditions beyond those listed in Table 23 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4.6 V for input currents less than 100 mA and periods shorter than 20 ns. (4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically. (5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (6) Typical values are for TA = 25° C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V. (7) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, and 1.5 V). (8) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO. (9) Drive strength is programmable according to values in Table 14 on page 55. (10) The Cyclone LVDS interface requires a resistor network outside of the transmitter channels. (11) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within ±0.5 pF. Power Consumption Detailed power consumption information for Cyclone devices will be released when available. Timing Model The DirectDrive technology and MultiTrack interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Cyclone device densities and speed grades. This section describes and specifies the performance, internal, external, and PLL timing specifications. All specifications are representative of worst-case supply voltage and junction temperature conditions. Preliminary & Final Timing Timing models can have either preliminary or final status. The Quartus II software issues an informational message during the design compilation if the timing models are preliminary. Table 39 shows the status of the Cyclone device timing models. Table 38. Cyclone Device Capacitance Note (11) Symbol Parameter Typical Unit CIO Input capacitance for user I/O pin 4.0 pF CLVDS Input capacitance for dual-purpose LVDS/user I/O pin 4.7 pF CVREF Input capacitance for dual-purpose VREF/user I/O pin. 12.0 pF CDPCLK Input capacitance for dual-purpose DPCLK/user I/O pin. 4.4 pF CCLK Input capacitance for CLK pin. 4.7 pF |
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