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EP1C12F100I7 Datasheet(PDF) 72 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 72 Page - Altera Corporation |
72 / 94 page 72 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information Table 35. SSTL-3 Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit VCCIO Output supply voltage 3.0 3.3 3.6 V VTT Termination voltage VREF – 0.05 VREF VREF + 0.05 V VREF Reference voltage 1.3 1.5 1.7 V VIH High-level input voltage VREF + 0.2 VCCIO + 0.3 V VIL Low-level input voltage –0.3 VREF – 0.2 V VOH High-level output voltage IOH = –8 mA (9) VTT + 0.6 V VOL Low-level output voltage IOL = 8 mA (9) VTT – 0.6 V Table 36. SSTL-3 Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Unit VCCIO Output supply voltage 3.0 3.3 3.6 V VTT Termination voltage VREF – 0.05 VREF VREF + 0.05 V VREF Reference voltage 1.3 1.5 1.7 V VIH High-level input voltage VREF + 0.2 VCCIO + 0.3 V VIL Low-level input voltage –0.3 VREF – 0.2 V VOH High-level output voltage IOH = –16 mA (9) VTT + 0.8 V VOL Low-level output voltage IOL = 16 mA (9) VTT – 0.8 V Table 37. Bus Hold Parameters Parameter Conditions VCCIO Level Unit 1.5 V1.8 V2.5 V3.3 V Min Max Min Max Min Max Min Max Low sustaining current VIN > VIL (maximum) 30 50 70 µA High sustaining current VIN < VIH (minimum) –30 –50 –70 µA Low overdrive current 0 V < VIN < VCCIO 200 300 500 µA High overdrive current 0 V < VIN < VCCIO –200 –300 –500 µA |
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