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EP1C12F100I7 Datasheet(PDF) 61 Page - Altera Corporation

Part # EP1C12F100I7
Description  Cyclone FPGA Family
Download  94 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I7 Datasheet(HTML) 61 Page - Altera Corporation

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Altera Corporation
61
Preliminary Information
Cyclone FPGA Family Data Sheet
Cyclone devices support reconfiguring the I/O standard settings on the
IOE through the JTAG BST chain. The JTAG chain can update the I/O
standard for all input and output pins any time before or during user
mode. Designers can use this ability for JTAG testing before configuration
when some of the Cyclone pins drive or receive from other devices on the
board using voltage-referenced standards. Since the Cyclone device might
not be configured before JTAG testing, the I/O pins might not be
configured for appropriate electrical standards for chip-to-chip
communication. Programming those I/O standards via JTAG allows
designers to fully test I/O connection to other devices.
The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The
TDO pin voltage is determined by the VCCIO of the bank where it resides.
The bank VCCIO selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or
3.3-V compatible.
Cyclone devices also use the JTAG port to monitor the operation of the
device with the SignalTapII embedded logic analyzer. Cyclone devices
support the JTAG instructions shown in Table 18.


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