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EP1C12F100I7 Datasheet(PDF) 57 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 57 Page - Altera Corporation |
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57 / 94 page  Altera Corporation 57 Preliminary Information Cyclone FPGA Family Data Sheet Advanced I/O Standard Support Cyclone device IOEs support the following I/O standards: ■ 3.3-V LVTTL/LVCMOS ■ 2.5-V LVTTL/LVCMOS ■ 1.8-V LVTTL/LVCMOS ■ 1.5-V LVCMOS ■ 3.3-V PCI ■ LVDS ■ SSTL-2 class I and II ■ SSTL-3 class I and II ■ Differential SSTL-2 class II (on output clocks only) Table 15 describes the I/O standards supported by Cyclone devices. Notes to Table 15: (1) EP1C3 devices do not support PCI. (2) EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O standard. (3) This I/O standard is only available on output clock pins (PLL_OUT pins). Cyclone devices contain four I/O banks, as shown in Figure 35. I/O banks 1 and 3 support all the I/O standards listed in Table 15. I/O banks 2 and 4 support all the I/O standards listed in Table 15 except the 3.3-V PCI standard. I/O banks 2 and 4 contain dual-purpose DQS, DQ, and DM pins to support a DDR SDRAM or FCRAM interface. I/O bank 1 can also support a DDR SDRAM or FCRAM interface, however, the configuration input pins in I/O bank 1 must operate at 2.5 V. I/O bank 3 can also support a DDR SDRAM or FCRAM interface, however, all the JTAG pins in I/O bank 3 must operate at 2.5 V. Table 15. Cyclone I/O Standards I/O Standard Type Input Reference Voltage (VREF) (V) Output Supply Voltage (VCCIO) (V) Board Termination Voltage (VTT) (V) 3.3-V LVTTL/LVCMOS Single-ended N/A 3.3 N/A 2.5-V LVTTL/LVCMOS Single-ended N/A 2.5 N/A 1.8-V LVTTL/LVCMOS Single-ended N/A 1.8 N/A 1.5-V LVCMOS Single-ended N/A 1.5 N/A 3.3-V PCI (1) Single-ended N/A 3.3 N/A LVDS (2) Differential N/A 2.5 N/A SSTL-2 class I and II Voltage-referenced 1.25 2.5 1.25 SSTL-3 class I and II Voltage-referenced 1.5 3.3 1.5 Differential SSTL-2 (3) Differential 1.25 2.5 1.25 |
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