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EP1C12F100I7 Datasheet(PDF) 52 Page - Altera Corporation |
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EP1C12F100I7 Datasheet(HTML) 52 Page - Altera Corporation |
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52 / 94 page  52 Altera Corporation Cyclone FPGA Family Data Sheet Preliminary Information DDR SDRAM & FCRAM Cyclone devices have dedicated circuitry for interfacing with DDR SDRAM. All I/O banks support DDR SDRAM and FCRAM I/O pins. However, the configuration input pins in bank 1 must operate at 2.5 V because the SSTL-2 VCCIO level is 2.5 V. Additionally, the configuration output pins (nSTATUS and CONF_DONE) and all the JTAG pins in I/O bank 3 must operate at 2.5 V because the VCCIO level of SSTL-2 is 2.5 V. I/O banks 1, 2, 3, and 4 support DQS signals with DQ bus modes of ×8. For ×8 mode, there are up to eight groups of programmable DQS and DQ pins, I/O banks 1, 2, 3, and 4 each have two groups in the 324-pin and 400-pin FineLine BGA packages. Each group consists of one DQS pin, a set of eight DQ pins, and one DM pin (see Figure 33). Each DQS pin drives the set of eight DQ pins within that group. Figure 33. Cyclone Device DQ & DQS Groups in ×8 Mode Note (1) Note to Figure 33: (1) Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin. DQ Pins DQS Pin DM Pin Top, Bottom, Left, or Right I/O Bank |
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