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FAN7930C Datasheet(PDF) 17 Page - ON Semiconductor |
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FAN7930C Datasheet(HTML) 17 Page - ON Semiconductor |
17 / 22 page ![]() www.onsemi.com 17 PCB Layout Guide PFC block nor mally handles high sw itching current and the voltage low energy signal path can be affected by the high energy path. Cautious PCB layout is mandatory for stable operation. 1. The gate drive path should be as short as possible. The closed-loop that starts from the gate driver, MOSFET gate, and MOSFET source to ground of PFC controller should be as close as possible. This is also crossing point betw een pow er ground and signal ground. Pow er ground path from the bridge diode to the output bulk capacitor should be short and w ide. The shar ing position betw een pow er ground and signal ground should be only at one position to avoid ground loop noise. Signal path of the PFC controller should be short and w ide for external components to contact. 2. The PFC output voltage sensing resistor is nor mally high to reduce current consumption. This path can be affected by external noise. To reduce noise potential at the INV pin, a shorter path for output sensing is recommended. If a shorter path is not possible, place some dividing resistors betw een PFC output and the INV pin — closer to the INV pin is better. Relative high voltage close to the INV pin can be helpful. 3. The Z CD path is recommended close to auxiliary w inding from boost inductor and to the Z CD pin. If that is difficult, place a s mall capac itor (below 50 pF) to reduce noise. 4. The sw itching current sense path should not share w ith another path to avoid interference. Some additional components may be needed to reduce the noise level applied to the CS pin. 5. A stabilizing capacitor for VCC is recommended as close as possible to the VCC and ground pins. If it is difficult, place the SMD capacitor as c lose to the corresponding pins as possible. Figure 44. Recom m ended PCB Layout |
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Similar Description - FAN7930C |
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