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FAN7930B Datasheet(PDF) 12 Page - ON Semiconductor

Part # FAN7930B
Description  Critical Conduction Mode PFC Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

FAN7930B Datasheet(HTML) 12 Page - ON Semiconductor

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12
Since the tw o OVP conditions are quite different,
protection recovering mode is different. Once the first
OV P triggers, sw itching stops immediately and recovers
sw itching w hen the output voltage is decreased w ith a
hysteresis. When the second OV P triggers, sw itching
can be recovered only w hen the VCC supply voltage falls
below VSTOP and builds up higher than VSTART again and
VOVP should be low er than hysteresis. If the second
OV P is not used, the OV P pin must be connected to the
INV pin or to the ground.
VCC
VINV
VOVP
IMOSFET
t
INV OVP
Level
hysteresis
Switching stop
only during
OVP
Error on INV
Resistors
Happens
OVP Level
VSTOP
VSTART
Switching stop
until VCC drops
below VSTOP and
recovers to
VSTART
If error
still exist,
OVP
triggers
again
OVP Level
Though Output-
Voltage Reduced,
no Switching.
Figure 25.
Com parison of First and Second
OVP Recovery Modes
4. Control Range Com pensation: On time is controlled
by the output voltage compensator w ith FA N7930B. Due
to this w hen input voltage is high and load is light,
control range becomes narrow compared to w hen input
voltage is low . That control range decrease is inversely
proportional to the double square of the input voltage
(
).
Thus
at
high
line,
unw anted burst operation easily happens at light load
and audible noise may be generated from the boost
inductor or inductor at input filter. Different from the
other converters, burst operation in PFC block is not
needed because the PFC block itself is nor mally
disabled dur ing standby mode. To reduce unw anted
burst operation at light load, an internal control range
compensation function is implemented and show s no
burst operation until 5% load at high line.
5. Zero-Current
Detection: Zero-current detection
(ZCD) generates the turn-on signal of the MOSFET
w hen the boost inductor current reaches zero using an
auxiliary w inding coupled w ith the inductor. When the
pow er sw itch turns on, negative voltage is induced at the
auxiliary w inding due to the opposite w inding direction
(see Equation 1). Positive voltage is induced (see
Equation 2) w hen the pow er sw itch turns off :
AC
IND
AUX
AUX
V
T
T
V
(1)
AC
PFCOUT
IND
AUX
AUX
V
V
T
T
V
(2)
w here VAUX is the auxiliary winding voltage; TIND and TAUX
are boost inductor turns and auxiliary w inding turns,
respectively; VAC is input voltage for PFC converter; and
VOUT_PFC is output voltage from the PFC converter.
PFC Inductor
Aux. Winding
VIN
PFC
VOUT
PFC
ZCD
VTH(ZCD)
+
-
VCC
THD
Optimized
Sawtooth
Generator
Restart
Timer
Gate
Driver
RZCD
CZCD
Negative Clamp
Circuit
Positive Clamp
Circuit
5
S
Q
R
Q
fMAX
Limit
Optional
Figure 26.
Circuit Near ZCD
Because auxiliary w inding voltage can sw ing from
negative to positive voltage, the internal block in Z CD
pin has both positive and negative voltage clamping
circuits. When the auxiliary voltage is negative, an
internal c ircuit c lamps the negative voltage at the Z CD
pin around 0.65 V by sourcing current to the serial
resistor betw een the ZCD pin and the auxiliary w inding.
When the auxiliary voltage is higher than 6.5 V, current
is sinked through a res istor from the auxiliary w inding to
the ZCD pin.
ISW
VAUX & VZCD
VACIN
IMOSFET
IDIODE
VAUX
VZCD
t
6.2V
0.65V
Figure 27.
Auxiliary Voltage Depends
on MOSFET Sw itching
The aux iliary w inding voltage is used to check the boost
inductor current zero instance. When boost inductor
current becomes zero, there is a resonance betw een
boost inductor and all capacitors at the MOSFET drain
pin, inc luding
COSS of the
MOSFET; an external
capacitor at the D-S pin to reduce the voltage rising and
falling slope of the MOSFET; a parasitic capacitor at
inductor; and so on to improve performance. Resonated
voltage is reflected to the auxiliary w inding and can be
used for detecting zero current of boost inductor and
valley position of MOSFET voltage stress. For valley
detection, a minor delay by the resistor and capacitor is
needed. A capacitor increases the noise immunity at the
ZCD pin. If Z CD voltage is higher than 1.5 V, an internal
ZCD comparator output becomes HIGH and LOW w hen
the ZCD goes below 1.4 V. At the falling edge of
comparator output, internal logic turns on the MOSFET.


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