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FAN4868 Datasheet(PDF) 10 Page - ON Semiconductor

Part # FAN4868
Description  3 MHz, Synchronous TinyBoost Regulator
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

FAN4868 Datasheet(HTML) 10 Page - ON Semiconductor

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FAN4868
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10
Table 10. MAXIMUM CEFF FOR FIRST−PASS
STARTUP
Operating Conditions
CEFF(MAX) (mF)
VIN (V)
RLOAD(MIN) (W)
3.3 VOUT
> 2.3
16
10
> 2.7
16
15
> 2.7
20
22
CEFF values shown in Table 10 typically apply to the
lowest VIN. The presence of higher VIN enhances ability to
start into larger CEFF at full load.
Transient Protection
To protect against external voltage transients caused by
ESD discharge events, or improper external connections,
some applications employ an external transient voltage
suppressor (TVS) and Schottky diode (D1 in Figure 19).
Figure 19. FAN4868 with External
Transient Protection
CIN
EN
SW
L1
GND
VIN
FB
VOUT
D1
Connector
C2
C1
B2
B1
A2
A1
VIN
COUT2
1 μH
4.7 μF
COUT
2.2 μF
The TVS is designed to clamp the FB line (system VOUT)
to +10 V or –2 V during external transient events. The
Schottky diode protects the output devices from the positive
excursion. The FB pin can tolerate up to 14 V of positive
excursion, while both the FB and VOUT pins can tolerate
negative voltages.
The FAN4868 includes a circuit to detect a missing or
defective D1 by comparing VOUT to FB. If VOUT – FB >
about 0.7 V, the IC shuts down. The IC remains shut down
until VOUT < UVLO and VIN < UVLO + 0.7 or EN is
toggled.
COUT2 may be necessary to preserve load transient
response when the Schottky is used. When a load is applied
at the FB pin, the forward voltage of the D1 rapidly increases
before the regulator can respond or the inductor current can
change. This causes an immediate drop of up to 300 mV,
depending on D1’s characteristics if COUT2 is absent. COUT2
supplies instantaneous current to the load while the regulator
adjusts the inductor current. A value of at least half of the
minimum value of COUT should be used for COUT2. COUT2
needs to withstand the maximum voltage at the FB pin as the
TVS is clamping.
The maximum DC output current available is reduced
with this circuit, due to the additional dissipation of D1.
LAYOUT GUIDELINE
Figure 20. WLCSP Suggested Layout (Top View)


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