14

AT572D740

7001AS–DPS–03/04

tional banked working registers, r8_fiq to r12_fiq, to enhance interrupt processing

speed.

The ARM7TDMI processor operates in little-endian mode.

To speed-up critical routine execution or critical data segment access, the ARM7 is

equipped with 32 Kbyte of zero wait states on-chip memory.

The ARM system has two buses. The main bus is the ASB (ARM System Bus). The

APB (ARM Peripheral Bus) is designed for accesses to on-chip peripherals. The AMBA

Bridge provides an interface between the ASB and the APB.

The D740 is equipped with a set of peripherals controlled by the ARM. An on-chip

Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPI and

the on- and off-chip memories in the DMA without the intervention of the processor.

Most importantly, the PDC removes the processor interrupt handling overhead and sig-

nificantly reduces the number of clock cycles required for data transfer.

Each peripheral has a 16K-byte address space allocated in the upper 3M bytes of the

4Gbyte address space. The peripheral register set is composed of control, mode, data,

status, and interrupt registers. To maximize the efficiency of bit manipulation, frequently

written registers are mapped into three memory locations.

A short description of the available peripherals is given in the following.

•

EBI (External Bus Interface): the EBI generates the signals that control the access

to the External Memory or peripheral devices.

•

ADDA (Analog to Digital and Digital to Analog interface): the ADDA provides 4

channel serial interface toward stereo audio 24-bit ADC and DAC.

•

PDC (Peripheral Data Controller): The PDC provides 8 communication channels

dedicated to the two USARTs and to the two SPIs. One PDC channel is connected

to the receiving channel and the one to the transmitting channel of each peripheral.

•

USART (Universal Synchronous / Asynchronous Receiver / Transmitter): two, full-

duplex, universal synchronous/asynchronous receiver/transmitters provide a simple

standard communication way managed by the Peripheral Data Controller.

•

SPI (Serial Peripheral Interface): two four-wire serial interfaces provide a simple

industry-standard communication way managed by the Peripheral Data Controller.

•

AIC (Advanced Interrupt Controller): the AIC is an 8-level priority, individually-

maskable, vectored interrupt controller. The interrupt controller is connected to the

NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the

ARM7TDMI processor.

•

PIO (Parallel I/O Controller): The PIO features 32 programmable I/O lines, 28 PIO

lines are available on D740 pads, while the remaining 4 are only internal.

•

TC (Timer Counter): the TC contains three identical 16-bit timer/counter channels.

•

WD (Watchdog Timer): the WD can be used to guard against system lock-up if the

software becomes trapped in a deadlock. If an overflow occurs, the watchdog timer

generates processor interrupts via the Advanced Interrupt Controller (AIC) and an

external low pulse through the PIO.

•

CLKGEN (Clock Generator): The clock generator provides divided clocks for several

peripherals: the Timer Counter, the Watchdog, the USARTs and the SPIs.