13

AT572D740

7001AS–DPS–03/04

ARM side the available bandwidth is limited by the bus size of the ARM processor (32

bits) giving a bandwidth of 4 bytes per ARM clock cycle.

ARM interface (mAAr)

The D740 master is the ARM7 RISC processor. mAgic behaves as a standard AMBA

ASB slave device, allowing access to different resources depending on the operating

mode (Run or System).

In System Mode, mAgic halts its execution and the ARM takes control of it. When mAgic

is in System mode the ARM can access many mAgic internal devices. The ability of the

ARM to access internal mAgic resources in System Mode can be used for initialization

and debugging purposes. By accessing the Command Register, the ARM can change

the operating status of the DSP (Run/System Mode), initiate DMA transactions, force

single or multiple step execution, or simply read the DSP operating status.

In Run Mode, mAgic works under direct control of its own VLIW program and the ARM

has access only to the 1K x 40-bit dual ported shared memory (PARM) and to the mAgic

Command Register.

In order to allow a tight coupling between the operations of mAgic and the ARM at run

time, they can exchange synchronization signals, based on interrupts.

ARM System: ARM7TDMI

Processor and

Peripherals

The ARM7TDMI is a 32-bit RISC microprocessor; it is a member of the Advanced RISC

Machines (ARM) family of general-purpose 32-bit microprocessors, offering high perfor-

mance and very low power consumption.

The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles,

and the instruction set and related decode mechanism are much simpler than those of

microprogrammed Complex Instruction Set Computers. This simplicity results in a high

instruction throughput and a real-time interrupt response. Pipelining is employed so that

all parts of the processing and memory systems can operate continuously. The typical

operating scheme of the ARM7TDMI is the sequence fetch-decode-execute.

The ARM7TDMI processor employs the architectural strategy known as THUMB.

THUMB instructions operate with the standard ARM register configuration, allowing

excellent interoperability between ARM and THUMB states. Each 16-bit THUMB

instruction has a corresponding 32-bit ARM instruction with the same effect on the pro-

cessor model. The 16-bit instructions are expanded at run time with no degradation of

the system performance. This provides far better performance than a 16-bit architecture,

with better code density than a 32-bit architecture.

The ARM7TDMI processor is built around a bank of 37 32-bit registers and six status

registers. The ARM7TDMI supports seven operation modes:

1.

User (usr): The normal ARM program execution state

2.

FIQ (fiq): Fast Interrupt reQuest; it is connected to the mAgic Halt signal

3.

IRQ (irq): Used for general-purpose interrupt handling

4.

Supervisor (svc): Protected mode for the operating system

5.

Abort mode (abt): Entered after data or instruction prefetch abort

6.

System (sys): A privileged user mode for the operating system

7.

Undefined (und):Entered when an undefined instruction is executed

Mode changes can be made under software control or can be brought about by external

interrupts or exception processing. Most application programs execute in User mode.

The non-user modes - known as privileged modes – are entered in order to service

interrupts or exceptions, or to access protected resources. Each operating mode has

dedicated banked registers for fast exception handling. The FIQ mode has five addi-