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TJR1441 Datasheet(PDF) 17 Page - NXP Semiconductors |
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TJR1441 Datasheet(HTML) 17 Page - NXP Semiconductors |
17 / 31 page NXP Semiconductors TJR1441 High-speed CAN transceiver TJR1441 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 7 September 2020 17 / 31 11 Dynamic characteristics Table 9. Dynamic characteristics Tvj = −40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJR1441A); RL = 60 Ω; unless specified otherwise. All voltages are defined with respect to ground.[1] Symbol Parameter Conditions Min Typ Max Unit CAN timing characteristics; tbit(TXD) ≥ 200 ns; see Figure 8, Figure 9 and Figure 14 td(TXD-busdom) delay time from TXD to bus dominant Normal mode - - 102.5 ns td(TXD-busrec) delay time from TXD to bus recessive Normal mode - - 102.5 ns td(busdom-RXD) delay time from bus dominant to RXD Normal or Silent mode - - 127.5 ns td(busrec-RXD) delay time from bus recessive to RXD Normal or Silent mode - - 127.5 ns td(TXDL-RXDL) delay time from TXD LOW to RXD LOW Normal mode - - 230 ns td(TXDH-RXDH) delay time from TXD HIGH to RXD HIGH Normal mode - - 230 ns CAN FD timing characteristics; see Figure 9 and Figure 14 tbit(TXD) = 500 ns 435 - 530 ns tbit(bus) transmitted recessive bit width tbit(TXD) = 200 ns 155 - 210 ns tbit(TXD) = 500 ns 400 - 550 ns tbit(RXD) bit time on pin RXD tbit(TXD) = 200 ns 120 - 220 ns tbit(TXD) = 500 ns -65 - 40 ns Δtrec receiver timing symmetry tbit(TXD) = 200 ns -45 - 15 ns Dominant time-out time; pin TXD tto(dom)TXD TXD dominant time-out time VTXD = 0 V; Normal mode [2] [3] 0.8 - 9 ms Mode transitions tt(moch) mode change transition time [2] - - 50 µs tstartup start-up time [2] - - 1 ms IO filter; pins S (TJR1441A/B), S_N (TJR1441D) and OFF (TJR1441D) tfltr(IO) I/O filter time [4] 1 - 5 µs Undervoltage detection; see Figure 4, Figure 5 and Figure 6 tdet(uv) undervoltage detection time on pin VCC [2] - - 30 µs on pin VCC; TJR1441B/D [2] - - 30 µs tuvd(swoff) switch-off undervoltage detection time on pin VIO; TJR1441A [2] - - 30 µs trec(uv) undervoltage recovery time on pin VCC [2] - - 50 µs [1] All parameters are guaranteed over the junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage ranges. [2] Not tested in production; guaranteed by design. [3] Time-out occurs between the min and max values. Time-out is guaranteed not to occur below the min value; time-out is guaranteed to occur above the max value. [4] Pulses shorter than the min value are guaranteed to be filtered out; pulses longer than the max value are guaranteed to be processed. |
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