TJR1441 datasheet(16/31 Pages) NXP

Part #	TJR1441

Description	High-speed CAN transceiver

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Manufacturer	NXP [NXP Semiconductors]

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NXP Semiconductors

TJR1441

High-speed CAN transceiver

TJR1441

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 7 September 2020

16 / 31

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Vrec(RX)

receiver recessive voltage

Normal or Silent mode;

-12 V ≤ VCANH ≤ +12 V;

-12 V ≤ VCANL ≤ +12 V

-4

-

0.5

V

Vdom(RX)

receiver dominant voltage

Normal or Silent mode;

-12 V ≤ VCANH ≤ +12 V;

-12 V ≤ VCANL ≤ +12 V

0.9

-

9

V

Vhys(RX)dif

differential receiver

hysteresis voltage

Normal or Silent mode;

-12 V ≤ VCANH ≤ +12 V;

-12 V ≤ VCANL ≤ +12 V

50

-

mV

IO(sc)

short-circuit output current

-15 V ≤ VCANH ≤ +40 V;

-15 V ≤ VCANL ≤ +40 V

-

115

mA

IO(sc)rec

recessive short-circuit output

current

Normal mode; VTXD = VIO[3];

-27 V ≤ VCANH ≤ +32 V;

-27 V ≤ VCANL ≤ +32 V

-3

-

+3

mA

IL

leakage current

VCC = VIO = 0 V or pins shorted to GND

via 47 KΩ; VCANH = VCANL = 5 V;

-10

-

+10

µA

Ri

input resistance

-2 V ≤ VCANL ≤ +7 V;

-2 V ≤ VCANH ≤ +7 V

25

40

50

kΩ

ΔRi

input resistance deviation

0 V ≤ VCANL ≤ +5 V; 0 V ≤ VCANH ≤ +5 V

-3

-

+3

%

Ri(dif)

differential input resistance

-2 V ≤ VCANL ≤ +7 V;

-2 V ≤ VCANH ≤ +7 V

50

80

100

kΩ

Ci(cm)

common-mode input

capacitance

[4] -

-

20

pF

Ci(dif)

differential input capacitance

[4] -

-

10

pF

Temperature detection

Tj(sd)

shutdown junction

temperature

180

-

200

°C

Tj(sd)rel

release shutdown junction

temperature

175

-

195

°C

[1]

All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified

temperature and power supply voltage range.

[2]

Undervoltage is detected between min and max values. Undervoltage is guaranteed to be detected below min value and guaranteed not to be detected

above max value.

[3]

VCC in TJR1441B/D

[4]

Not tested in production; guaranteed by design.

[5]

The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 15

[6]

See Figure 10

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