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W25Q16JVSSIQ Datasheet(PDF) 24 Page - Winbond |
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W25Q16JVSSIQ Datasheet(HTML) 24 Page - Winbond |
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24 / 75 page  W25Q16JV - 23 - Write Disable (04h) The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving /CS l ow, shifting the instruction code “04h” into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase and Reset instructions. Figure 7. Write Disable Instruction Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1, “35h” for Status Register-2 or “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 8. Refer to section 7.1 for Status Register descriptions. The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 8. The instruction is completed by driving /CS high. Figure 8. Read Status Register Instruction /CS CLK DI (IO 0) DO (IO 1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Mode 0 Mode 3 Instruction (04h) High Impedance /CS CLK DI (IO0) DO (IO1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (05h/35h/15h) High Impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 Status Register-1/2/3 out Status Register-1/2/3 out * * = MSB * |
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