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W25Q16JVSSIQ Datasheet(PDF) 15 Page - Winbond |
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W25Q16JVSSIQ Datasheet(HTML) 15 Page - Winbond |
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15 / 75 page  W25Q16JV Publication Release Date: March 22, 2018, 2018 - 14 - Revision G Figure 4b. Status Register-2 Erase/Program Suspend Status (SUS) – Status Only The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle. Security Register Lock Bits (LB3, LB2, LB1) –Non-Volatile OTP Writable The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the Write Status Register instruction. LB3- 1 are One Time Programmable (OTP), once it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently. 8. QUAD ENABLE (QE) – Volatile/Non-Volatile Writable The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that enables Quad SPI operation. When the QE bit is set to a 0 state (factory default for part numbers with ordering options “IM” & “JM”), the /HOLD are enabled, the device operates in Standard/Dual SPI modes. When the QE bit is set to a 1 (factory fixed default for part numbers with ordering options “IQ” &”JQ”), the Quad IO2 and IO3 pins are enabled, and /HOLD function is disabled, the device operates in Standard/Dual/Quad SPI modes. S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP LB 3 LB 2 LB 1 (R ) QE SR L Status Register Lock (Volatile/Non-Volatile Writable) Complement Protect (Volatile/Non-Volatile Writable) Security Register Lock Bits (Non-Volatile OTP Writable) Reserved Quad Enable (Volatile/Non-Volatile Writable) Suspend Status (Status-Only) |
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