 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
W25Q16JVSSIQ Datasheet(PDF) 12 Page - Winbond |
|
|
|||||||||||||||||||||||||||||
W25Q16JVSSIQ Datasheet(HTML) 12 Page - Winbond |
|
|
12 / 75 page  W25Q16JV - 11 - 7. STATUS AND CONFIGURATION REGISTERS Three Status and Configuration Registers are provided for W25Q16JV. The Read Status Register-1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program Suspend status, and output driver strength. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks, and output driver strength. Write access to the Status Register is controlled by the state of the non- volatile Status Register Protect bits (SRL), the Write Enable instruction, and during Standard/Dual SPI operations. 7.1 Status Registers Figure 4a. Status Register-1 Erase/Write In Progress (BUSY) – Status Only BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions. Write Enable Latch (WEL) – Status Only Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register. Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected. SRP SEC TB BP2 BP1 BP0 WEL BUSY TOP/BOTTOM PROTECT WRITE ENABLE LATCH S7 S6 S5 S4 S3 S2 S1 S0 STATUS REGISTER PROTECT SECTOR PROTECT BLOCK PROTECT BITS WRITE IN PROGRESS (volatile/non-volatile) (volatile/non-volatile) (volatile/non-volatile) (volatile/non-volatile) |
Similar Part No. - W25Q16JVSSIQ |
|
Similar Description - W25Q16JVSSIQ |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
