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W25Q16JVSSIQ Datasheet(PDF) 57 Page - Winbond |
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W25Q16JVSSIQ Datasheet(HTML) 57 Page - Winbond |
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57 / 75 page  W25Q16JV Publication Release Date: March 22, 2018, 2018 - 56 - Revision G Enable Reset (66h) and Reset Device (99h) Because of the small package and the limitation on the number of pins, the W25Q16JV provide a software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going internal operations will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Read parameter setting (P7-P0), and Wrap Bit setting (W6-W4). “Enable Reset (66h)” and “Reset (99h)” instructions can be issued in SPI mode. To avoid accidental reset, both instructions must be issued in sequence. Any other commands other than “Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset command is accepted by the device, the device will take approximately tRST=30us to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Figure 58. Enable Reset and Reset Instruction Sequence Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (99h) Mode 0 Mode 3 /CS CLK DI (IO 0) DO (IO 1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (66h) High Impedance |
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