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W25Q16JVSSIQ Datasheet(PDF) 51 Page - Winbond |
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W25Q16JVSSIQ Datasheet(HTML) 51 Page - Winbond |
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51 / 75 page  W25Q16JV Publication Release Date: March 22, 2018, 2018 - 50 - Revision G Program Security Registers (42h) The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Program Security Register Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. ADDRESS A23-16 A15-12 A11-8 A7-0 Security Register #1 00h 0 0 0 1 0 0 0 0 Byte Address Security Register #2 00h 0 0 1 0 0 0 0 0 Byte Address Security Register #3 00h 0 0 1 1 0 0 0 0 Byte Address The Program Security Register instruction sequence is shown in Figure 46. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Program Security Register instruction to that register will be ignored (See 7.1.8, 8.2.25 for detail descriptions). Figure 46. Program Security Registers Instruction /CS CLK DI (IO 0) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (42h) 8 9 10 28 29 30 39 24-Bit Address 23 22 21 3 2 1 * /CS CLK DI (IO 0) 40 41 42 43 44 45 46 47 Data Byte 2 48 49 50 52 53 54 55 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 Data Byte 1 7 6 5 4 3 2 1 * Mode 0 Mode 3 Data Byte 3 0 Data Byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = MSB * |
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