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W25Q16JVSSIQ Datasheet(PDF) 49 Page - Winbond |
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W25Q16JVSSIQ Datasheet(HTML) 49 Page - Winbond |
49 / 75 page W25Q16JV Publication Release Date: March 22, 2018, 2018 - 48 - Revision G Read SFDP Register (5Ah) The W25Q16JV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about device configurations, available instructions and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified, but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications, as well as the JEDEC standard JESD216-serials that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet. The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah” followed by a 24-bit address (A23-A0)(1) into the DI pin. Eight “dummy” clocks are also required before the SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB) first as shown in Figure 44. For SFDP register values and descriptions, please refer to the Winbond Application Note for SFDP Definition Table. Note 1: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register. Figure 44. Read SFDP Register Instruction Sequence Diagram /CS CLK DI (IO 0) DO (IO 1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (5Ah) High Impedance 8 9 10 28 29 30 31 24-Bit Address 23 22 21 3 2 1 0 Data Out 1 * /CS CLK DI (IO 0) DO (IO 1) 32 33 34 35 36 37 38 39 Dummy Byte High Impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 Data Out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = MSB * |
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