W25Q16JVSSIQ datasheet(39/75 Pages) WINBOND

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W25Q16JVSSIQ Datasheet(PDF) 39 Page - Winbond

Part #	W25Q16JVSSIQ

Description	3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI

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Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

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39 / 75 page

W25Q16JV

Publication Release Date: March 22, 2018, 2018

- 38 -

Revision G

Chip Erase (C7h / 60h)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write

Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status

instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 34.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase

instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence

for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read

Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1

during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other

instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status

by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.

Figure 34. Chip Erase Instruction

/CS

CLK

(IO

Mode 0

Mode 3

Instruction (C7h/60h)

High Impedance

Mode 0

Mode 3

Manufacturer	Part #	Datasheet	Description
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Manufacturer	Part #	Datasheet	Description
Winbond	W25Q16CV	1Mb / 79P	3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI
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	W25Q16DVUUIG-TR	1Mb / 80P	3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI
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Shenzhen Huazhimei Semi...	HM25Q64A	13Mb / 76P	3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL, QUAD SPI
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Winbond	W25Q32JVSFIQ-TR	932Kb / 78P	3V 32M-BIT SERIAL FLASH MEMORY WITH DUAL, QUAD SPI

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