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LP8866S-Q1 Datasheet(PDF) 22 Page - Texas Instruments |
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LP8866S-Q1 Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 82 page  + ± R Q Q S VREF R2 GM + ± CURRENT RAMP GENERATOR COMP + ± GM OVP OCP TSD R1 COUT CIN PGND ISNS ISNSGND FB GD CPUMP VIN VOUT Pulse Generator + ± + ± + ± VOVPH VOVPL VUVP BSTOVPH BSTOVPL BSTOCP ISEL[10:0] R3 R4 CCOMP Figure 7-7. External Compensation Network This network will create one additional pole and one additional zero in the loop. > @ 1 4 ( 1 || ) S POLE_COMP 2 COMP f = 2 R R R C (12) 4 1 S ZERO_COMP COMP f = 2 R C (13) It could be noted that R3 doesn't take part in the compensation. So this external compensation network could be both used in two-divider netwrok and T-divider network with no equation change. In real application, for example, when DC-DC loop has stability concern, putting the additional pole in 1 kHz and the additional zero in 2 kHz will suppress the loop gain by approximately 6 dB after 2 kHz. This will benefit gain margin and phase margin a lot. 7.3.6.4 Boost Sync and Spread Spectrum Spread spectrum function could be enabled when BST_SYNC pin is high and disabled when BST_SYNC pin is low. If an external CLK signal is on the BST_SYNC pin, the boost controller can be clocked by this signal. If the clock disappears later, the boost continues operation at the frequency defined by RBST_FSET resistor, and the spread spectrum function will be enabled or disabled depending on the final pin level of BST_SYNC. Table 7-3. Boost Synchronization Mode BST_SYNC PIN LEVEL BOOST CLOCK MODE Low (GND) Spread spectrum disabled High (VDDIO) Spread spectrum enabled LP8866S-Q1 SNVSBD1A – AUGUST 2020 – REVISED FEBRUARY 2021 www.ti.com 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8866S-Q1 |
Similar Part No. - LP8866S-Q1_V01 |
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Similar Description - LP8866S-Q1_V01 |
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