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LP8866S-Q1 Datasheet(PDF) 14 Page - Texas Instruments |
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LP8866S-Q1 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 82 page  7.2 Functional Block Diagram Charge Pump VDD Powerline FET Control Boost Controller GD PGND ISNS ISNSGND + ± FB Discharge OSC 20 MHz OTP ADC PWM_FSET BST_FSET EN PWM BST_SYNC INT SDA SCL I2C DISCHARGE LED Current Setting OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 LED_GND ISET VSENSE_N VSENSE_P SD Analog Blocks VREF, TSD MODE SGND BOOST CONTROL C1N C1P CPUMP UVLO LED_SET 7.3 Feature Description 7.3.1 Control Interface Device control interface includes: • EN is the enable input for the LP8866S-Q1 device. • PWM is the default input to control the brightness of all current sinks by duty cycle. • INT is an open-drain fault output indicating fault condition detection. • SDA and SCL are data and clock line for I2C interface to control the brightness of all current sinks and read back the fault conditions for diagnosis. • BST_SYNC is used to input an external clock for the boost switching frequency and control the internal boost clock mode. – The external clock is auto detected at start-up and, if missing, the internal clock is used. LP8866S-Q1 SNVSBD1A – AUGUST 2020 – REVISED FEBRUARY 2021 www.ti.com 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8866S-Q1 |
Similar Part No. - LP8866S-Q1_V01 |
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Similar Description - LP8866S-Q1_V01 |
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