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LP8866S-Q1 Datasheet(PDF) 11 Page - Texas Instruments |
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LP8866S-Q1 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 82 page  Limits apply over the full operation temperature range –40°C ≤ TA ≤ +125°C , unless otherwise speicified. VIN = 12 V, VDD = 5 V, VEN = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VENIL EN logic low threshold 0.4 V VENIH EN logic high threshold 1.2 V RENPD EN pin internal pull down resistance 1 MΩ LOGIC INPUT SDA, SCL, BST_SYNC and PWM VIL Logic low threshold VDD = 3.3 V and 5 V 0.4 V VIH Logic high threshold VDD = 3.3 V and 5 V 1.2 V LOGIC OUTPUT SDA, INT VOL Output level low I = 3 mA 0.2 0.4 V ILEAKAGE Output leakage current V = 3.3 V 1 µA 6.7 Timing Requirements for I2C Interface Limits apply over the full operation temperature range –40°C ≤ TA ≤ +125°C , unless otherwise speicified. VIN = 12 V, VDD = 5 V, VEN = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCLK Clock frequency 400 kHz 1 Hold time (repeated) START condition 0.6 µs 2 Clock low time 1.3 µs 3 Clock high time 600 ns 4 Set-up time for a repeated START condition 600 ns 5 Data hold time 50 ns 6 Data setup time 100 ns 7 Rise time of SDA and SCL 300 ns 8 Fall time of SDA and SCL 300 ns 9 Set-up time for STOP condition 600 ns 10 Bus free time between a STOP and a START condition 1.3 µs 8 1 7 6 8 3 2 5 4 1 SCL SDA 9 7 10 Figure 6-1. I2C Timing Diagram www.ti.com LP8866S-Q1 SNVSBD1A – AUGUST 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LP8866S-Q1 |
Similar Part No. - LP8866S-Q1_V01 |
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Similar Description - LP8866S-Q1_V01 |
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