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LP8866S-Q1 Datasheet(PDF) 80 Page - Texas Instruments |
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LP8866S-Q1 Datasheet(HTML) 80 Page - Texas Instruments |
80 / 82 page www.ti.com EXAMPLE BOARD LAYOUT 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND 38X (1.5) 38X (0.3) 36X (0.5) (5.8) (R0.05) TYP (3.4) NOTE 9 (9.7) NOTE 9 ( 0.2) TYP VIA (2.9) (4.7) (1.2) (0.6) TYP 3X (1.2) PowerPAD TSSOP - 1.2 mm max height DCP0038A SMALL OUTLINE PACKAGE 4218816/A 10/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 8X SYMM SYMM 1 19 20 38 METAL COVERED BY SOLDER MASK SOLDER MASK DEFINED PAD SEE DETAILS 39 15.000 METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED SOLDER MASK DEFINED |
Similar Part No. - LP8866S-Q1_V01 |
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Similar Description - LP8866S-Q1_V01 |
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