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LP8866S-Q1 Datasheet(PDF) 70 Page - Texas Instruments |
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LP8866S-Q1 Datasheet(HTML) 70 Page - Texas Instruments |
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70 / 82 page  10 Layout 10.1 Layout Guidelines Figure 10-1 shows a layout recommendation for the LP8866S-Q1 used to illustrate the principles of good layout. This layout can be adapted to the actual application layout if and where possible. It is important that all boost components are close to each other and to the chip; the high-current traces must be wide enough. VDD must be as noise-free as possible. Place a VDD bypass capacitor near the VDD and GND pins. A charge-pump capacitor, boost input capacitors, and boost output capacitors must have closest VIAs to GND. Place the charge-pump capacitors close to the device. The main points to guide the PCB layout design: • Current loops need to be minimized: – For low frequency the minimal current loop can be achieved by placing the boost components as close as possible to each other. Input and output capacitor grounds need to be close to each other to minimize current loop size. – Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact under the current traces. High frequency return currents follow the route with minimum impedance, which is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when return current flows just under the positive current route in the ground plane, if the ground plane is intact under the route. – For high frequency the copper area capacitance must be taken into account. For example, the copper area for the drain of boost N-MOSFET is a tradeoff between capacitance and the cooling capacity of the components. • GND plane must be intact under the high-current-boost traces to provide shortest possible return path and smallest possible current loops for high frequencies. • Route boost output voltage (VOUT) to LEDs, FB pin & Discharge pin after output capacitors not straight from the diode cathode. • FB network should be placed as close as possible to the FB pin, not near boost output • A small bypass capacitor (TI recommends a 39-pF capacitor) could be placed close to the FB pin and GND to suppress high frequency noise • VDD line must be separated from the high current supply path to the boost converter to prevent high frequency ripple affecting the chip behavior. • Capacitor connected to charge pump output CPUMP is recommended to have 10-µF capacitance. This capacitor must be as close as possible to CPUMP pin. This capacitor provides a greater peak current for gate driver and must be used even if the charge pump is disabled. If the charge pump is disabled, the VDD and CPUMP pins must be tied together. • Input and output capacitors need low-impedance grounding (wide traces with many vias to GND plane). • Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to become unstable under certain load conditions. DC bias characteristics should be obtained from the component manufacturer; DC bias is not taken into account on component tolerance. LP8866S-Q1 SNVSBD1A – AUGUST 2020 – REVISED FEBRUARY 2021 www.ti.com 70 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8866S-Q1 |
Similar Part No. - LP8866S-Q1_V01 |
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Similar Description - LP8866S-Q1_V01 |
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