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LP8866S-Q1 Datasheet(PDF) 69 Page - Texas Instruments |
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LP8866S-Q1 Datasheet(HTML) 69 Page - Texas Instruments |
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69 / 82 page  Table 8-7. Recommended Components for SEPIC Design Example REFERENCE DESIGNATOR DESCRIPTION NOTE RISENSE 20 mΩ, 1 W Input current sensing resistor RSD 20 kΩ, 0.1 W Power-line FET gate pullup resistor RSENSE 50 mΩ, 1 W Boost current sensing resistor RG 15 Ω, 0.1 W Gate resistor to control the rising/falling time of nMOSFET for EMC RUVLO1 76.8 kΩ, 0.1 W These UVLO resistor settings set the VIN_UVLO rising voltage at 3.75 V, VIN_UVLO falling voltage at 3.35 V RUVLO2 20.5 kΩ, 0.1 W RFB2 60 kΩ, 0.1 W Bottom feedback divider resistor RFB1 330 kΩ, 0.1 W Top feedback divider resistor RBST_FSET 124 kΩ, 0.1 W Boost frequency set resistor (2200 kHz) RISET 38.7 kΩ, 0.1 W Current set resistor (80 mA per channel) RPWM_FSET 4.75 kΩ, 0.1 W Output PWM frequency set resistor (305-Hz PWM frequency) RMODE 3.92 kΩ, 0.1 W Mode resistor (Phase-Shift PWM mode with 0x2B I2C address) RLED_SET 4.75 kΩ, 0.1 W LED_SET resistor (5 channels configuration) CPUMP 10-µF, 10-V ceramic Charge-pump output capacitor C2X 2.2-µF, 10-V ceramic Flying capacitor CVDD 4.7-µF + 0.1-µF, 10-V ceramic VDD bypass capacitor CIN 1 × 33-µF, 50-V electrolytic + 1 × 10-µF, 50-V ceramic Boost input capacitor COUT 1 × 33-µF, 50-V electrolytic + 1 × 10-µF, 50-V ceramic Boost output capacitor CS1 10-µF, 50-V ceramic SEPIC coupling capacitor CS2 33-µF, 50-V electrolytic SEPIC coupling capacitor RS 2 Ω, 0.125 W SEPIC resistor L1 4.7-µH saturation current 3 A SEPIC inductor L2 4.7-µH saturation current 3 A SEPIC inductor D1 50-V 10-A Schottky diode SEPIC Schottky diode Q1 60-V, 25-A nMOSFET SEPIC nMOSFET Q2 60-V, 30-A pMOSFET Power-line FET 8.2.3.3 Application Curves See Application Curves. 9 Power Supply Recommendations The LP8866S-Q1 is designed to operate from a car battery. The VIN input must be protected from reverse voltage and voltage dump condition over 48 V. The impedance of the input supply rail must be low enough that the input current transient does not cause drop below VIN UVLO level. If the input supply is connected with long wires, additional bulk capacitance may be required in addition to normal input capacitor. The voltage range for VDD is 3 V to 5.5 V. A ceramic capacitor must be placed as close as possible to the VDD pin. The boost gate driver is powered from the CPUMP pins. A ceramic capacitor must be placed as close to the CPUMP pins as possible. www.ti.com LP8866S-Q1 SNVSBD1A – AUGUST 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: LP8866S-Q1 |
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