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LP8866S-Q1 Datasheet(PDF) 31 Page - Texas Instruments |
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LP8866S-Q1 Datasheet(HTML) 31 Page - Texas Instruments |
31 / 82 page L FB VSENSE_P VDD ISNSGND VIN COUT ISNS GD CIN VSENSE_N SD PGND VOUT 3 to 48V SGND 3.3V/5V UVLO R4 R5 Figure 7-16. VIN UVLO Setting Circuit The following equation is used to calculate the UVLO threshold for VIN rising edge: ) 4 UVLO_RISING UVLO_TH 5 R VIN = ( 1 VIN R u (16) where • VINUVLO_TH = 0.787 V The hysteresis of UVLO threshold can be designed and calculated with the following equation. HYST 4 UVLO VIN = I R u (17) where • IUVLO = 5 µA So the following equation can be used for UVLO threshold for VIN falling edge: UVLO_FALLING UVLO_RISING HYST VIN = VIN -VIN (18) The bottom resistors, R5 of voltage divider is able to be disconnected to the GND through an additional external N-type of FET as Figure 7-17. This design is to minimize the current leakage from VIN in shutdown mode to extend the battery life. www.ti.com LP8866S-Q1 SNVSBD1A – AUGUST 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LP8866S-Q1 |
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