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LP8866S-Q1 Datasheet(PDF) 30 Page - Texas Instruments |
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LP8866S-Q1 Datasheet(HTML) 30 Page - Texas Instruments |
30 / 82 page 100 Hz Input PWM 1.2 kHz LED PWM Without Dither 50.00225% 1.2 kHz LED PWM With 3bit Dither 50% 50% 50% 50% 50.006% 50.006% 50.006% 50% 50% 50% 50% 50% 50% 50% 50% 50% Figure 7-14. PWM Dither Example The dither block also helps in low brightness scenario when dimming ratio is limited by LED PWM output frequency and the LED output pulse is less than the minimum pulse width (200 ns). In such scenario, the dither block will skip some of the PWM pulses to reduce the brightness further, enabling high dimming ratio. The end result is that the LED PWM frequency is reduced as more and more minimum pulses are skipped or dithered out. At the same time, dither block will also guarantee that the minimum LED PWM frequency is not less than 152 Hz to ensure no brightness flickering. Figure 7-15 shows how the dither works in low brightness scenario. 100 Hz Input PWM 305 Hz LED PWM With Minimum Pulse Dither 300 ns = 0.003% 200 ns 3.2 ms No Pulse 3.2 ms 200 ns 3.2 ms 3.2 ms No Pulse 300 ns = 0.003% Average Brightness = 0.003% Figure 7-15. Minimum Brightness Dither Example 7.3.9 Protection and Fault Detections The LP8866S-Q1 device includes fault detections for LED open, short and short-to-GND conditions, boost input undervoltage, overvoltage and overcurrent, boost output overvoltage and overcurrent, VDD undervoltage, die overtemperature and external components. The host can monitor the status of the faults in registers SUPPLY_FAULT_STATUS, BOOST_FAULT_STATUS and LED_STATUS. 7.3.9.1 Supply Faults 7.3.9.1.1 VIN Undervoltage Faults (VINUVLO) The LP8866S-Q1 device supports VIN undervoltage and overvoltage protection. The undervoltage threshold is programmable through external resistor divider on UVLO pin. If during operation of the LP8866S-Q1 device, the UVLO pin voltage falls below the UVLO falling level (0.787 V typical), the boost, LED outputs, and power-line FET will be turned off, and the device will enter STANDBY mode. The VINUVLO_STATUS bit is also set in the SUPPLY_FAULT_STATUS register, and the INT pin is triggered. When the UVLO voltage rises above the rising threshold level the LP8866S-Q1 exits STANDBY and begins the start-up sequence. LP8866S-Q1 SNVSBD1A – AUGUST 2020 – REVISED FEBRUARY 2021 www.ti.com 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8866S-Q1 |
Similar Part No. - LP8866S-Q1_V01 |
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Similar Description - LP8866S-Q1_V01 |
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