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UPD70F3114 Datasheet(PDF) 10 Page - NEC |
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UPD70F3114 Datasheet(HTML) 10 Page - NEC |
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10 / 692 page  10 User’s Manual U15195EJ5V0UD 4.3.1 Chip select control function.......................................................................................................... 82 4.4 Bus Cycle Type Control Function ........................................................................................... 85 4.5 Bus Access ................................................................................................................................ 86 4.5.1 Number of access clocks............................................................................................................. 86 4.5.2 Bus sizing function....................................................................................................................... 87 4.5.3 Bus width ..................................................................................................................................... 88 4.6 Wait Function............................................................................................................................. 94 4.6.1 Programmable wait function ........................................................................................................ 94 4.6.2 External wait function .................................................................................................................. 96 4.6.3 Relationship between programmable wait and external wait ....................................................... 96 4.7 Idle State Insertion Function.................................................................................................... 97 4.8 Bus Priority Order ..................................................................................................................... 98 4.9 Boundary Operation Conditions.............................................................................................. 99 4.9.1 Program space ............................................................................................................................ 99 4.9.2 Data space .................................................................................................................................. 99 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION ................................................................ 100 5.1 SRAM, External ROM, External I/O Interface........................................................................ 100 5.1.1 Features .................................................................................................................................... 100 5.1.2 SRAM, external ROM, external I/O access ............................................................................... 101 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) ................................................................... 105 6.1 Features ................................................................................................................................... 105 6.2 Configuration........................................................................................................................... 106 6.3 Control Registers .................................................................................................................... 107 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) ............................................................. 107 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3)....................................................... 109 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)................................................................ 111 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) ................................................... 112 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)........................................................ 114 6.3.6 DMA disable status register (DDIS)........................................................................................... 116 6.3.7 DMA restart register (DRST) ..................................................................................................... 116 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) ............................................................. 117 6.4 Transfer Modes........................................................................................................................ 120 6.4.1 Single transfer mode ................................................................................................................. 120 6.4.2 Single-step transfer mode.......................................................................................................... 122 6.4.3 Block transfer mode................................................................................................................... 123 6.5 Transfer Types......................................................................................................................... 123 6.5.1 Two-cycle transfer ..................................................................................................................... 123 6.6 Transfer Target ........................................................................................................................ 124 6.6.1 Transfer type and transfer target ............................................................................................... 124 6.6.2 External bus cycles during DMA transfer (two-cycle transfer) ................................................... 125 6.7 DMA Channel Priorities .......................................................................................................... 125 6.8 Next Address Setting Function.............................................................................................. 125 6.9 DMA Transfer Start Factors ................................................................................................... 127 6.10 Forcible Suspension ............................................................................................................... 128 6.11 DMA Transfer End ................................................................................................................... 128 |
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