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UPD70F3114 Datasheet(PDF) 64 Page - NEC |
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UPD70F3114 Datasheet(HTML) 64 Page - NEC |
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64 / 692 page  CHAPTER 3 CPU FUNCTION 64 User’s Manual U15195EJ5V0UD (3) On-chip peripheral I/O area 4 KB of memory, addresses FFFF000H to FFFFFFFH, are provided as an on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen in the area between addresses 3FFF000H and 3FFFFFFH Note. Note Access to the area of addresses 3FFF000H to 3FFFFFFH is prohibited. To access the on-chip peripheral I/O, specify addresses FFFF000H to FFFFFFFH. FFFFFFFH FFFF000H On-chip peripheral I/O area (4 KB) On-chip peripheral I/O registers associated with the operation mode specification and the state monitoring for the on-chip peripheral I/O are all memory-mapped to the on-chip peripheral I/O area. Program fetches cannot be executed from this area. Cautions 1. The least significant bit of an address is not decoded. Therefore, if byte access is executed in the register at an odd address (2n + 1), the register at the even address (2n) will be accessed because of the hardware specification. 2. In the V850E/IA2, no registers exist that are capable of word access, but if a register is word accessed, halfword access is performed twice in the order of lower address, then higher address of the word area, ignoring the lower 2 bits of the address. 3. For registers in which byte access is possible, if halfword access is executed, the higher 8 bits become undefined during the read operation, and the lower 8 bits of data are written to the register during the write operation. 4. Addresses that are not defined as registers are reserved for future expansion. If these addresses are accessed, the operation is undefined and not guaranteed. 5. Addresses 3FFF000H to 3FFFFFFH cannot be specified as the source/destination address of DMA transfer. Be sure to use addresses FFFF000H to FFFFFFFH for the source/destination address of DMA transfer. (4) External memory area 4 MB are available for external memory area. • Single-chip mode: x100000H to x3FFFFFH • ROMless mode: x000000H to x3FFFFFH Note that the internal ROM, internal RAM, and on-chip peripheral I/O areas cannot be accessed as external memory areas. |
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