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UPD70F3114 Datasheet(PDF) 62 Page - NEC |
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UPD70F3114 Datasheet(HTML) 62 Page - NEC |
62 / 692 page CHAPTER 3 CPU FUNCTION 62 User’s Manual U15195EJ5V0UD (b) Interrupt/exception table The V850E/IA2 increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request is acknowledged, execution jumps to the handler address, and the program written at that memory location is executed. Table 3-3 shows the sources of interrupts/exceptions, and the corresponding addresses. Remark When in ROMless mode, in order to resume correct operation after reset, provide a handler address to the reset routine at address 0 of the external memory. Table 3-3. Interrupt/Exception Table Start Address of Interrupt/Exception Table Interrupt/Exception Source Start Address of Interrupt/Exception Table Interrupt/Exception Source 00000000H RESET 00000230H INTP24/INTCC24 00000010H NMI0 00000240H INTP25/INTCC25 00000040H TRAP0n (n = 0 to F) 00000250H INTTM3 00000050H TRAP1n (n = 0 to F) 00000260H INTP30/INTCC30 00000060H ILGOP/DBG0 00000270H INTP31/INTCC31 00000080H INTP0 00000280H INTCM4 00000090H INTP1 00000290H INTDMA0 000000A0H INTP2 000002A0H INTDMA1 000000B0H INTP3 000002B0H INTDMA2 000000C0H INTP4 000002C0H INTDMA3 000000F0H INTDET0 00000310H INTCSI0 00000100H INTDET1 00000320H INTCSI1 00000110H INTTM00 00000330H INTSR0 00000120H INTCM003 00000340H INTST0 00000130H INTTM01 00000350H INTSER0 00000140H INTCM013 00000360H INTSR1 00000150H INTP100/INTCC100 00000370H INTST1 00000160H INTP101/INTCC101 000003A0H INTAD0 00000170H INTCM100 000003B0H INTAD1 00000180H INTCM101 000003F0H INTCM010 000001D0H INTTM20 00000400H INTCM011 000001E0H INTTM21 00000410H INTCM012 000001F0H INTP20/INTCC20 00000420H INTCM014 00000200H INTP21/INTCC21 00000430H INTCM015 00000210H INTP22/INTCC22 00000440H INTCM004 00000220H INTP23/INTCC23 00000450H INTCM005 |
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