UPD70F3114 datasheet(46/692 Pages) NEC

Part #	UPD70F3114

Description	32-Bit Single-Chip Microcontrollers

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46

User’s Manual U15195EJ5V0UD

CHAPTER 3 CPU FUNCTION

The CPU of the V850E/IA2 is based on RISC architecture and executes almost all instructions in one clock cycle,

using 5-stage pipeline control.

3.1

Features

• Minimum instruction execution time: 25 ns (@ internal 40 MHz operation)

• Memory space

Program space: 64 MB linear

Data space:

4 GB linear

• Thirty-two 32-bit general-purpose registers

• Internal 32-bit architecture

• Five-stage pipeline control

• Multiplication/division instructions

• Saturated operation instructions

• One-clock 32-bit shift instruction

• Load/store instructions in long/short format

• Four types of bit manipulation instructions

• SET1

• CLR1

• NOT1

• TST1

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