ESMT

M12L64164A

Elite Semiconductor Memory Technology Inc.

Publication Date: Nov. 2005

Revision: 2.6

1/44

SDRAM

1M x 16 Bit x 4 Banks

Synchronous DRAM

FEATURES

JEDEC standard 3.3V power supply

LVTTL compatible with multiplexed address

Four banks operation

MRS cycle with address key programs

- CAS Latency (2 & 3)

- Burst Length (1, 2, 4, 8 & full page)

- Burst Type (Sequential & Interleave)

All inputs are sampled at the positive going edge of the

system clock

DQM for masking

Auto & self refresh

15.6

ORDERING INFORMATION

54 Pin TSOP (Type II)

(400mil x 875mil )

PRODUCT NO.

MAX FREQ. PACKAGE

Comments

M12L64164A-5TG

200MHz

TSOP II

Pb-free

M12L64164A-6TG

166MHz

TSOP II

Pb-free

M12L64164A-7TG

143MHz

TSOP II

Pb-free

GENERAL DESCRIPTION

The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by

16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on

every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high performance memory system applications.

PIN ASSIGNMENT

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

LDQ M

WE

CAS

RAS

CS

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

NC

UD Q M

CLK

CKE

NC