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UPD784938 Datasheet(PDF) 13 Page - NEC |
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UPD784938 Datasheet(HTML) 13 Page - NEC |
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13 / 733 page  13 Preliminary User’s Manual U13987EJ1V0UM00 CONTENTS CHAPTER 1 GENERAL ........................................................................................................................... 39 1.1 Features .................................................................................................................................... 41 1.2 Ordering Information ............................................................................................................... 42 1.3 Pin Configuration (Top View) ................................................................................................. 43 1.3.1 Normal operation mode ............................................................................................................... 43 1.4 Application System Configuration Example (Car Audio (Tuner, Deck)) .......................... 45 1.5 Block Diagram .......................................................................................................................... 46 1.6 List of Functions ...................................................................................................................... 47 1.7 Differences among Products in µPD784938 Subseries ..................................................... 50 1.8 Main Differences with µPD784908 Subseries ...................................................................... 50 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 51 2.1 Pin Function Lists .................................................................................................................... 51 2.1.1 Normal operation mode ............................................................................................................... 51 2.2 Pin Functions ........................................................................................................................... 55 2.2.1 Normal operation mode ............................................................................................................... 55 2.3 Input/Output Circuits and Connection of Unused Pins ..................................................... 62 2.4 Cautions .................................................................................................................................... 65 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 67 3.1 Memory Space .......................................................................................................................... 67 3.2 Internal ROM Area .................................................................................................................... 73 3.3 Base Area .................................................................................................................................. 74 3.3.1 Vector table area .......................................................................................................................... 75 3.3.2 CALLT instruction table area ....................................................................................................... 76 3.3.3 CALLF instruction entry area ...................................................................................................... 76 3.4 Internal Data Area .................................................................................................................... 77 3.4.1 Internal RAM area ........................................................................................................................ 78 3.4.2 Special function register (SFR) area ........................................................................................... 81 3.4.3 External SFR area ....................................................................................................................... 81 3.5 External Memory Space .......................................................................................................... 81 3.6 µPD78F4938 Memory Mapping............................................................................................... 82 3.7 Control Registers ..................................................................................................................... 83 3.7.1 Program counter (PC) .................................................................................................................. 83 3.7.2 Program status word (PSW) ........................................................................................................ 83 3.7.3 Use of RSS bit ............................................................................................................................. 86 3.7.4 Stack pointer (SP) ........................................................................................................................ 88 3.8 General-Purpose Registers .................................................................................................... 92 3.8.1 Configuration ................................................................................................................................92 3.8.2 Functions ...................................................................................................................................... 94 3.9 Special Function Registers (SFR) ......................................................................................... 97 3.10 Cautions .................................................................................................................................... 103 CHAPTER 4 CLOCK GENERATOR ...................................................................................................... 105 4.1 Configuration and Function ................................................................................................... 105 |
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