 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPD784938 Datasheet(PDF) 84 Page - NEC |
|
|
|||||||||||||||||||||||||||||
UPD784938 Datasheet(HTML) 84 Page - NEC |
|
|
84 / 733 page  84 CHAPTER 3 CPU ARCHITECTURE Preliminary User’s Manual U13987EJ1V0UM00 (2) Parity/overflow flag (P/V) The P/V flag performs the following two kinds of operation associated with execution of an operation instruction. The status of the P/V flag can be tested with a conditional branch instruction. • Parity flag operation Set (to 1) when the number of bits set (to 1) as the result of execution of a logical operation instruction, shift/rotate instruction, or a CHKL or CHKLA instruction is even, and reset (to 0) if odd. When a 16-bit shift instruction is executed, however, only the low-order 8 bits of the operation result are valid for the parity flag. • Overflow flag operation Set (1) only when the numeric range expressed as a two’s complement is exceeded as the result of execution of a arithmetic operation instruction, and reset (to 0) otherwise. More specifically, the value of this flag is the exclusive OR of the carry into the MSB and the carry out of the MSB. For example, the two’s complement range in an 8-bit arithmetic operation is 80H (–128) to 7FH (+127), and the flag is set (to 1) if the operation result is outside this range, and reset (to 0) if within this range. Example The operation of the overflow flag when an 8-bit addition instruction is executed is shown below. When the addition of 78H (+120) and 69H (+105) is performed, the operation result is E1H (+225), and the two’s complement limit is exceeded, with the result that the P/V flag is set (to 1). Expressed as a two’s complement, E1H is -31. 78H (+120) = 0111 1000 +) 69H (+105) = +) 0110 1001 0 1110 0001 = –31 P/V = 1 ↑ CY When the following two negative numbers are added together, the operation result is within the two’s complement range, and therefore the P/V flag is reset (to 0). FBH (–5) = 1111 1011 +) F0H (–16) = +) 1111 0000 1 1110 1011 = –21 P/V = 0 ↑ CY (3) Interrupt request enable flag (IE) This flag controls CPU interrupt request acknowledgment operations. When “0”, interrupts are disabled, and only non-maskable interrupts and unmasked macro service can be acknowledged. All other interrupts are disabled. When “1”, the interrupt enabled state is set, and enabling of interrupt request acknowledgment is controlled by the interrupt mask flags corresponding to the individual interrupt requests and the priority of the individual interrupts. The IE flag is set (to 1) by execution of an EI instruction, and reset (to 0) by execution of a DI instruction or acknowledgment of an interrupt. |
Similar Part No. - UPD784938 |
|
Similar Description - UPD784938 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
