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UPD784938 Datasheet(PDF) 77 Page - NEC |
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UPD784938 Datasheet(HTML) 77 Page - NEC |
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77 / 733 page  77 CHAPTER 3 CPU ARCHITECTURE Preliminary User’s Manual U13987EJ1V0UM00 3.4 Internal Data Area The internal data area consists of the internal RAM area and special function register area (see Figures 3-1, 3-2, and 3-3). The final address of the internal data area can be specified by means of the LOCATION instruction as either 0FFFFH (when a LOCATION 0 instruction is executed) or FFFFFH (when a LOCATION 0FH instruction is executed). Selection of the addresses of the internal data area by means of the LOCATION instruction must be executed once immediately after reset release, and once the selection is made, it cannot be changed. The program after reset release must be as shown in the example below. If the internal data area and another area are allocated to the same addresses, the internal data area is accessed and the other area cannot be accessed. Example RSTVCT CSEG AT 0 DW RSTSTRT to INITSEG CSEG BASE RSTSTRT: LOCATION 0H; or LOCATION 0FH MOVG SP, #STKBGN Caution When the LOCATION 0 instruction is executed, it is necessary to ensure that the program after reset release does not overlap the internal data area. It is also necessary to make sure that the entry addresses of the service routines for non-maskable interrupts such as NMI do not overlap the internal data area. Also, initialization must be performed for maskable interrupt entry areas, etc., before the internal data area is referenced. |
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