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UPD784938 Datasheet(PDF) 73 Page - NEC |
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UPD784938 Datasheet(HTML) 73 Page - NEC |
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73 / 733 page  73 CHAPTER 3 CPU ARCHITECTURE Preliminary User’s Manual U13987EJ1V0UM00 3.2 Internal ROM Area The µPD784938 Subseries products shown below incorporate ROM which is used to store programs, table data, etc. If the internal ROM area and internal data area overlap when the LOCATION 0 instruction is executed, the internal data area is accessed, and the overlapping part of the internal ROM area cannot be accessed. Part Number Internal ROM Address Space LOCATION 0 Instruction LOCATION 0FH Instruction µPD784935 96 Kbytes × 8 bits 00000H to 0EAFFH 00000H to 17FFFH 10000H to 17FFFH µPD784936 128 Kbytes × 8 bits 00000H to 0E4FFH 00000H to 1FFFFH 10000H to 1FFFFH µPD784937 192 Kbytes × 8 bits 00000H to 0DEFFH 00000H to 2FFFFH 10000H to 2FFFFH µPD784938 256 Kbytes × 8 bits 00000H to 0D5FFH 00000H to 3FFFFH µPD78F4938 10000H to 3FFFFH The internal ROM can be accessed at high speed. Normally, fetches are performed at the same speed as external ROM, but if the IFCH bit of the memory expansion mode register (MM) is set (to 1), the high-speed fetch function is used and internal ROM fetches are performed at high speed (2-byte fetch performed in 2 system clocks). When the instruction execution cycle equal to an external ROM fetch is selected, wait insertion is performed by the wait function, but when high-speed fetches are used, wait insertion is not performed for internal ROM. RESET input sets the instruction execution cycle equal to the external ROM fetch cycle. |
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Similar Description - UPD784938 |
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