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UPD784938 Datasheet(PDF) 41 Page - NEC |
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UPD784938 Datasheet(HTML) 41 Page - NEC |
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41 / 733 page  CHAPTER 1 GENERAL 41 Preliminary User’s Manual U13987EJ1V0UM00 1.1 Features • 78K/IV Series • High-speed instruction execution • Minimum instruction execution time: 320 ns (@ 6.29-MHz operation) 160 ns (@ 12.58-MHz operation) • Instruction set suitable for control applications • Data memory expansion function (1-Mbyte memory space: 2 bank specification pointers) • Interrupt controller (4-level priority system) • Vectored interrupt service/macro service/context switching • Standby functions: HALT/STOP/IDLE modes • Internal memory: • ROM Mask ROM: 256 Kbytes ( µPD784938) 192 Kbytes ( µPD784937) 128 Kbytes ( µPD784936) 96 Kbytes ( µPD784935) Flash memory: 256 Kbytes ( µPD78F4938) • RAM: 10,240 bytes ( µPD784938, 78F4938) 8,192 bytes ( µPD784937) 6,656 bytes ( µPD784936) 5,120 bytes ( µPD784935) • I/O pins: 80 • Software programmable pull-up: 70 inputs • Direct LED drive capability: 24 outputs • Direct transistor drive capability: 8 outputs • N-ch open-drain: 4 outputs • Serial interface • UART/IOE (3-wire serial I/O): 2 channels (with on-chip baud rate generator) • CSI (3-wire serial I/O): 2 channels • Real-time output ports (combination with timer/counter allows independent control of 2-system stepping motors) • A/D converter (8-bit resolution × 8 channels) • PWM outputs (12-bit resolution × 2 channels) • On-chip simple model with IEBus controller • Watch timer (operation with main clock possible in the IDLE mode) • Power-saving regulator • High-performance timer/counter • Timer/event counter (16 bits) × 3 units • Timer (16 bits) × 1 unit • Watchdog timer: 1 channel • Clock output function: fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16 can be selected • On-chip ROM correction function |
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Similar Description - UPD784938 |
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