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UPD784938 Datasheet(PDF) 34 Page - NEC |
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UPD784938 Datasheet(HTML) 34 Page - NEC |
34 / 733 page ![]() 34 Preliminary User’s Manual U13987EJ1V0UM00 24-16 Refresh Area Specification Register (RFA) Format ................................................................................... 630 24-17 Pulse Refresh Operation in Internal Memory Access ................................................................................ 631 24-18 Refresh Pulse Output Operation ................................................................................................................. 632 24-19 Timing for Return from Self-Refresh Operation .......................................................................................... 633 24-20 Hold Mode Register (HLDM) Format .......................................................................................................... 634 24-21 Hold Mode Timing ........................................................................................................................................ 635 25-1 Standby Mode Transition Diagram .............................................................................................................. 637 25-2 Standby Function Block Diagram ................................................................................................................ 638 25-3 Standby Control Register (STBC) Format .................................................................................................. 640 25-4 Oscillation Stabilization Time Specification Register (OSTS) Format ....................................................... 641 25-5 STOP Mode Release by NMI Input ............................................................................................................. 648 25-6 STOP Mode Release by INTP4/INTP5 Input ............................................................................................. 649 25-7 Example of Address/Data Bus Processing ................................................................................................. 654 26-1 Reset Signal Acknowledgment .................................................................................................................... 657 26-2 Power-On Reset Operation ......................................................................................................................... 658 26-3 Reset Input Timing ....................................................................................................................................... 661 27-1 ROM Correction Block Diagram .................................................................................................................. 665 27-2 Memory Mapping Example ( µPD784938) ................................................................................................... 666 27-3 ROM Correction Address Register (CORAH, CORAL) Format ................................................................. 667 27-4 ROM Correction Control Register (CORC) Format .................................................................................... 668 28-1 Internal Memory Size Switching Register (IMS) Format ............................................................................ 672 28-2 Communication Mode Selection Format ..................................................................................................... 673 28-3 Flashpro II and Flashpro III Connection in 3-Wire Serial I/O Mode .......................................................... 675 28-4 Flashpro II and Flashpro III Connection in UART Mode ............................................................................ 675 A-1 Development Tool Configuration ................................................................................................................. 710 A-2 Package Drawing of EV-9200GF-100 (reference) (unit: mm) .................................................................... 718 A-3 Recommended Board Mounting Pattern of EV-9200GF-100 (reference) (unit: mm) ............................... 719 LIST OF FIGURES (12/12) Figure No. Title Page |
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