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UPD784938 Datasheet(PDF) 23 Page - NEC |
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UPD784938 Datasheet(HTML) 23 Page - NEC |
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23 / 733 page  23 Preliminary User’s Manual U13987EJ1V0UM00 2-1 Pin Input/Output Circuits ............................................................................................................................. 64 3-1 µPD784935 Memory Map ............................................................................................................................ 69 3-2 µPD784936 Memory Map ............................................................................................................................ 70 3-3 µPD784937 Memory Map ............................................................................................................................ 71 3-4 µPD784938, 78F4938 Memory Map ........................................................................................................... 72 3-5 Internal RAM Memory Map ......................................................................................................................... 79 3-6 Internal Memory Size Switching Register (IMS) ......................................................................................... 82 3-7 Program Counter (PC) Format .................................................................................................................... 83 3-8 Program Status Word (PSW) Format ......................................................................................................... 83 3-9 Stack Pointer (SP) Format .......................................................................................................................... 88 3-10 Data Saved to Stack Area ........................................................................................................................... 89 3-11 Data Restored from Stack Area .................................................................................................................. 90 3-12 General-Purpose Register Format .............................................................................................................. 92 3-13 General-Purpose Register Addresses ........................................................................................................ 93 4-1 Clock Generator Block Diagram .................................................................................................................. 105 4-2 Clock Oscillator External Circuitry .............................................................................................................. 106 4-3 Standby Control Register (STBC) Format .................................................................................................. 108 4-4 Oscillation Stabilization Time Specification Register (OSTS) Format ....................................................... 109 4-5 Signal Extraction with External Clock Input ................................................................................................ 111 4-6 Cautions on Resonator Connection ............................................................................................................ 112 4-7 Incorrect Example of Resonator Connection .............................................................................................. 113 5-1 Regulator Peripherals Block Diagram ......................................................................................................... 115 6-1 Port Configuration ........................................................................................................................................ 117 6-2 Port 0 Block Diagram ................................................................................................................................... 119 6-3 Port 0 Mode Register (PM0) Format ........................................................................................................... 120 6-4 Port Specified as Output Port ..................................................................................................................... 121 6-5 Port Specified as Input Port ........................................................................................................................ 122 6-6 Pull-Up Resistor Option Register L (PUOL) Format .................................................................................. 123 6-7 Pull-Up Resistor Specification (Port 0) ....................................................................................................... 124 6-8 Example of Transistor Drive ........................................................................................................................ 125 6-9 P12 (Port 1) Block Diagram ........................................................................................................................ 127 6-10 P13 (Port 1) Block Diagram ........................................................................................................................ 128 6-11 P14 (Port 1) Block Diagram ........................................................................................................................ 129 6-12 Block Diagram of P10, P11, and P15 to P17 (Port 1) ................................................................................ 130 6-13 Port 1 Mode Register (PM1) Format ........................................................................................................... 131 6-14 Port 1 Mode Control Register (PMC1) Format ........................................................................................... 131 6-15 Port Specified as Output Port ..................................................................................................................... 132 LIST OF FIGURES (1/12) Figure No. Title Page |
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